Web-based SPG290 / S+Core Emulator – Technical Feedback Welcome

[Ccor444]

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I’m currently developing an experimental web-based emulator written entirely in JavaScript, focused on the Sunplus SPG290 (S+Core RISC) architecture.
The project runs directly in the browser and already includes:
A CPU core with registers, flags, PC, instruction execution and cycle counting
MIU / memory mapping (RAM, ROM, Flash, IO regions)
An internal debugger console (LUNA) with commands such as:
step / run / pause / reset
register and memory inspection
disassembly and instruction tracing
breakpoints and watches
SPU (audio) subsystem with basic voice control
CD-ROM / ISO9660 support for loading and inspecting disc images
At the moment, video output (VDU rendering) is still under development, but the core system, execution loop and debugger infrastructure are already functional.
This project is mainly intended for:
learning and research
reverse engineering experiments
understanding SoC / embedded system emulation in a web environment
I would really appreciate technical feedback, especially regarding:
emulator architecture
CPU execution model
debugger design
memory mapping approaches
general best practices for accuracy and maintainability
Project link:
👉 https://ccor444.github.io/hyperscan-js-core/
Thank you for your time and any insights you’re willing to share.

[mecodeatlas]

Welcome to the GitHub Community, @Ccor444, we're happy you're here! You are more likely to get a useful response if you are posting your question in the applicable category and are explicit about what your project entails--giving a few more details might help someone give you a nudge in the right direction. I've gone ahead and moved it for you. Good luck!

[Ccor444]

I see that no one was interested in the project.